#ifndef PHAL_UART_CONFIG_H_
#define PHAL_UART_CONFIG_H_

#define UART0_ENABLE							FALSE

#define UART0_DATA_LENGTH						padl_uart_FDR_8_BITS

#define UART0_ENABLE_PARITY_CHECKING			FALSE

#define UART0_PARITY							padl_uart_FDR_ODD_PARITY

#define UART0_STOP_BIT							padl_uart_FDR_1_STOP_BIT

#define UART0_FRACTIONAL_BAUDRATE_DIVISOR		5

#define UART0_FRACTIONAL_BAUDRATE_MULTIPLIER	14

#define UART0_BAUDRATE_DIVISOR					12

#define UART0_ENABLE_INTERRUPT					TRUE

#define UART0_INTERRUPT_PRIORITY				15

#define UART0_ENABLE_DATA_TRANSMITTED_INTERRUPT			TRUE

#define UART0_DATA_TRANSMITTED_HANDLER					service_uart_txHandler

#define UART0_DATA_TRANSMITTED_ARG						((void*)0)

#define UART0_ENABLE_DATA_RECEIVED_INTERRUPT			TRUE

#define UART0_DATA_RECEIVED_HANDLER						service_uart_rxHandler

#define UART0_DATA_RECEIVED_ARG							((void*)0)

#define UART0_ENABLE_RECEIVING_DATA_ERROR_INTERRUPT		FALSE

#define UART0_RECEIVING_DATA_ERROR_HANDLER

#define UART0_RECEIVING_DATA_ERROR_ARG					((void*)0)




#define UART1_ENABLE							TRUE

#define UART1_DATA_LENGTH						padl_uart_FDR_8_BITS

#define UART1_ENABLE_PARITY_CHECKING			FALSE

#define UART1_PARITY							padl_uart_FDR_ODD_PARITY

#define UART1_STOP_BIT							padl_uart_FDR_1_STOP_BIT

#define UART1_FRACTIONAL_BAUDRATE_DIVISOR		5

#define UART1_FRACTIONAL_BAUDRATE_MULTIPLIER	14

#define UART1_BAUDRATE_DIVISOR					12

#define UART1_ENABLE_INTERRUPT					TRUE

#define UART1_INTERRUPT_PRIORITY				15

#define UART1_ENABLE_DATA_TRANSMITTED_INTERRUPT			TRUE

#define UART1_DATA_TRANSMITTED_HANDLER					service_uart_txHandler

#define UART1_DATA_TRANSMITTED_ARG						((void*)0)

#define UART1_ENABLE_DATA_RECEIVED_INTERRUPT			TRUE

#define UART1_DATA_RECEIVED_HANDLER						service_uart_rxHandler

#define UART1_DATA_RECEIVED_ARG							((void*)0)

#define UART1_ENABLE_RECEIVING_DATA_ERROR_INTERRUPT		FALSE

#define UART1_RECEIVING_DATA_ERROR_HANDLER				

#define UART1_RECEIVING_DATA_ERROR_ARG					((void*)1)




#define UART2_ENABLE							FALSE

#define UART2_DATA_LENGTH						padl_uart_FDR_8_BITS

#define UART2_ENABLE_PARITY_CHECKING			FALSE

#define UART2_PARITY							padl_uart_FDR_ODD_PARITY

#define UART2_STOP_BIT							padl_uart_FDR_1_STOP_BIT

#define UART2_FRACTIONAL_BAUDRATE_DIVISOR		5

#define UART2_FRACTIONAL_BAUDRATE_MULTIPLIER	14

#define UART2_BAUDRATE_DIVISOR					12

#define UART2_ENABLE_INTERRUPT					FALSE

#define UART2_INTERRUPT_PRIORITY				15

#define UART2_ENABLE_DATA_TRANSMITTED_INTERRUPT			FALSE

#define UART2_DATA_TRANSMITTED_HANDLER

#define UART2_DATA_TRANSMITTED_ARG

#define UART2_ENABLE_DATA_RECEIVED_INTERRUPT			FALSE

#define UART2_DATA_RECEIVED_HANDLER

#define UART2_DATA_RECEIVED_ARG

#define UART2_ENABLE_RECEIVING_DATA_ERROR_INTERRUPT		FALSE

#define UART2_RECEIVING_DATA_ERROR_HANDLER

#define UART2_RECEIVING_DATA_ERROR_ARG




#define UART3_ENABLE							FALSE

#define UART3_DATA_LENGTH						padl_uart_FDR_8_BITS

#define UART3_ENABLE_PARITY_CHECKING			FALSE

#define UART3_PARITY							padl_uart_FDR_ODD_PARITY

#define UART3_STOP_BIT							padl_uart_FDR_1_STOP_BIT

#define UART3_FRACTIONAL_BAUDRATE_DIVISOR		5

#define UART3_FRACTIONAL_BAUDRATE_MULTIPLIER	14

#define UART3_BAUDRATE_DIVISOR					12

#define UART3_ENABLE_INTERRUPT					FALSE

#define UART3_INTERRUPT_PRIORITY				15

#define UART3_ENABLE_DATA_TRANSMITTED_INTERRUPT			FALSE

#define UART3_DATA_TRANSMITTED_HANDLER

#define UART3_DATA_TRANSMITTED_ARG

#define UART3_ENABLE_DATA_RECEIVED_INTERRUPT			FALSE

#define UART3_DATA_RECEIVED_HANDLER

#define UART3_DATA_RECEIVED_ARG

#define UART3_ENABLE_RECEIVING_DATA_ERROR_INTERRUPT		FALSE

#define UART3_RECEIVING_DATA_ERROR_HANDLER

#define UART3_RECEIVING_DATA_ERROR_ARG

#endif /*PHAL_UART_CONFIG_H_*/
